1. Field of the Invention
The present invention relates to a memory circuit apparatus, particularly to a memory circuit apparatus including a memory cell array in which a discharge current flows through a common source line from precharged bit lines via selected memory cells at the time of read.
2. Description of the Related Art
A conventional non-volatile memory device described in U.S. Pat. No. 5,453,955, for example, includes read charging transistors for setting bit lines at a predetermined read potential to perform a data read operation, and read discharging transistors for setting non-selected bit lines at the ground potential during the read operation. A similar non-volatile memory device also described in U.S. Pat. No. 6,195,297.
In a data read operation of the non-volatile memory device, bit lines are first precharged and are subsequently set in a floating state, and then data items are read through the bit lines. When many selected cells are on-cells, many charges on the corresponding bit lines are discharged, so that a ground line should be designed to have a big capacity. This is a problem to be solved when a large-scale integration of a memory circuit apparatus is demanded.